The present invention relates to automatic digital test systems, particularly of the in-circuit type, for testing digital devices such as integrated circuits, and more particularly to a method and system for selectively loading test data into test data storage means associated with test pins of an automatic digital test system.
Automatic digital test systems used to test digital devices have become more and more sophisticated as the complexity of the devices tested by such systems has increased. Typical large scale integrated (LSI) circuits, for example, may require a rather complicated series of tests in order to insure that such circuits are fully operational. Accordingly, various methods for speeding up the test procedures have been developed in an effort to minimize test time as the devices increase in complexity. This effort to save test time has also been accompanied by efforts to reduce programming complexity and equipment costs while maintaining or even increasing the versatility of the automatic test equipment.
One area of particular interest has been that relating to the transfer of test signals to and from the drivers and comparators ("pin electronics") which stimulate and monitor the test pins connecting the tester to the component or device under test. For example, because of the speed constraints inherent in applying test signals to the pin electronics directly from the computer controlling the test operations, individual memories have been utilized to receive test signals from the computer and to then supply them directly to the pin electronics. In this manner, the patterns of test signals (vectors) for numerous test cycles can be stored in the individual memories and supplied rapidly to the to the pin electronics at a rate greater than that of the computer. A discussion of this problem is set forth in greater detail in U.S. patent application Ser. No. 312,839 filed Oct. 19, 1981 by the present inventor, and Ser. No. 307,322 filed Sept. 30, 1981 now U.S. Pat. No. 4,433,414 by Maurice Carey, both of which are assigned to the assignee of the present invention and are hereby incorporated herein by reference.
Typically, the test signals or test vectors are first transferred from the computer into an addressable memory. In one known system they are then supplied through the pin electronics to the appropriate test pins on the test fixture through relay multiplexing onto a fixed pattern of pins. In another known system, the stored test signals are transferred from the addressable memory by time domain multiplexing into a fixed pattern of pin memories and then through the pin electronics onto the individual pins. These approaches avoid the need to directly transfer test signals from the computer to the pin electronics at the computer rate. However, the slow response time of electro-mechanical relays in a relay multiplexing system necessitates that the selection of individual test pins be done between test of devices. The time domain multiplexing approach does not suffer from this slow relay response time, but the fixed nature of the test signal sequence presented to the individual pin memories detracts considerably from the versatility of such an approach. In particular, since the data for a group of pins are presented in a fixed, consecutive sequence, the data for the last pin memory must await entry of all other data before it can be entered even if there are no changes in the earlier presented data. This, of course, requires more time than it would to merely modify the contents of a single pin memory directly.